Course Syllabus 2014/2015
 
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Module : EN202
Title :
VHDL project
Number of hours :
Tutorial classes : 30.00 h
Individual work : 9.00 h
ECTS credits :
2.50
Evaluation :
Teacher(s) :
LE GAL Bertrand
RENAUD Sylvie - Responsible
BORNAT Yannick
JEGO Christophe
Shared by UV(s) :
Level :
second year module
Abstract :
During this projet, students design a digital system with Xilinx FPGA target. They use VHDL hardware description langage, Mentor Graphic ModelSim for simulation tool, and Xilinx ISE for syntheis and place and root tool.
Keyword(s) :
Digital systel design, FPGA, VHDL